In conventional integrated circuit memory devices, various kinds of pipeline structures have been used to increase the speed in a column output path. One example of such a pipeline structure is a wave pipeline structure in which a plurality of registers is used. The wave pipeline structure has a relatively simple circuit construction and operates at relatively high speed. As a result, wave pipeline structures are often used in synchronous integrated circuit memory devices.
FIG. 1 is a block diagram that illustrates a data output path in a conventional synchronous integrated circuit memory device and also illustrates a column output path in a read operation mode. Referring now to FIG. 1, a read command is input to the synchronous integrated circuit memory device. Next, memory cell data, which is respectively output through bit line sense amplifiers 2, 3, 4, 5, is provided to a corresponding local input/output line (LI0i: i ranging from 1 to 3) through each corresponding column selection transistor M1–M4 that respectively respond to column selection signals CSL0–CSL3 applied from a column address decoder (not shown). input/output sense amplifiers 6, 7, 8, 9 are respectively connected to the local input/output lines L100–L103 and are configured to amplify data provided to the local input/output lines L100–L103 and apply the amplified data to a multiplexer 10 connected to a global input/output line.
The multiplexer 10 multiplexes the data output from the input/output sense amplifiers 6, 7, 8, 9, and applies the data to a data output multiplexer 100. The data is transferred from the multiplexer 10 through one switch selected among a plurality of data line switches SF1–SF16 within the data output multiplexer 100. The data line switches SF1–SF16 are activated in response to a data line selection signal applied through data line selection signal lines DL0–DL3 and apply output data from the multiplexer 10 to a corresponding register. The output data respectively stored at the first through nth registers 101–116 are provided to input terminals of a plurality of register output selection switches S1–S16. When one of the register output selection switches S1–S16 is switched on by a switching selection signal, the data is provided onto a multiplexing output line.
The switching selection signals (CDQ0_F-CDQ7_F, CDQ0_S-CDQ7_S) are provided to the register output selection switches S1–S16 according to the timing diagram of FIG. 2. The switching selection signals (CDQ0_F-CDQ7_F) are generated in response to a first edge (a rising edge or a falling edge) of a clock signal CLK shown in FIG. 2. The switching selection signals (CDQ0_S-CDQ7_S) are generated in response to a second edge (a falling edge or a rising edge) of the clock CLK. FIG. 2 further illustrates a data output operation of the integrated circuit memory device of FIG. 1. Data (DOFi, DOSi) respectively representing the data on two multiplexing output lines are individually applied to input terminals of first and second data group selection switches SW1, SW2. When one of the first and second data group selection switches SW1, SW2 is switched on in response to group selection output switching signals (CLKDQ_F, CLKDQ_S) that are applied complementarily to one another, output data DOUT, which is synchronized to a clock, is output through an output pin PD1 connected to an output terminal of an output driver 30 as shown in FIG. 2.
As described above with respect to FIGS. 1 and 2, a function of the data output multiplexer 100 is to provide a double data rate DDB output operation. The data output circuit comprises the data output multiplexer 100 together with the first and second data group selection switches SW1, SW2 and the output driver 30. The data output multiplexer 100 is used to ensure a high-speed data output operation of about 500 MHz to reduce data skew and junction loading and/or wiring loading.
A conventional double data rate data output multiplexer 100 may have a wave pipeline structure as discussed above, but there is room for improvement in the art. Referring now to FIG. 3, switches S1–S4 are connected to the multiplexing output line DOFi. Each of the switches S1–S4 may comprise a CMOS transmission gate, but is illustrated herein as one MOS transistor for convenience. FIG. 3 also illustrates various signal lines coupled to the gate G, source S and drain D regions. As shown in FIG. 3, the multiplexing output line DOFi has four junction portions. Thus, the multiplexing output line DOFi within the data output multiplexer 100 of FIG. 1 has eight junction portions (eight switches S1 through S8). Because the junction loading on the multiplexing output lines DOFi and DOSi is relatively large, a data output time may be delayed.
FIG. 4 schematically shows lengths of wire lines (L1, L2, L3, and L4) that are disposed before/after the plurality of register output selection switches S1–S8 and the multiplexing output line L3. Referring now to FIG. 4, a length (D2a) of the wire line L2 is longer than a length (D1a) of the wire line L1, and a length (D3a) of the wire line L3 is also relatively long. In general, if a length of the wire line L2, which is made of metal, is relatively long, then a wire loading is concentrated onto a multiplexing output node and a data output may be delayed.
FIG. 5 shows a disposition relation between the plurality of register output selection switches S1–S16 and the first and second data group selection switches SW1, SW2. Wiring lengths of the multiplexing output lines DOFi, DOSi are different from each other. That is to say, a data output path PA1 passing through a first register 101, a data output path PA2 passing through an eighth register 108, and a data output path PA3 passing through an nth register 116, are all different from one another. Thus, data skew may occur.
FIGS. 6 and 7 respectively show a connection relation of the overlap prevention control signal lines CL1–CL5 for respectively providing complementary switching selection signals, which are applied to the register output selection switches S1–S16. For example, when the switch S1 of FIG. 6 is switched on, the switch S16 is switched off, and when the switch S2 is switched on, the switch S15 is switched off so as to prevent an overlap of data. If switch S1 is switched on by a high signal, a low signal inverted from the high signal is applied to the switch S16. The low signal functions as an overlap prevention control signal.
As shown in FIG. 6, a considerable difference in length exists between the overlap prevention control signal line CL1 and the overlap prevention control signal line CL3. Further, as shown in FIG. 7, only the overlap prevention control signal line CL1 is longer than other overlap prevention control signal lines CL2, CL3, CL4, CL5. Therefore, if the overlap prevention control signal lines have different lengths, a path difference may cause a multiplexing overlap of output data.